We have provided consultation to industry-leading companies on backplane and card designs based on various interface specifications, such as JESD204C, PCI-Express 2,3,4,5,6, HDMI, SATA2,3, SAS, USB3.1, XAUI, SFP, QSFP28, QSFPdd, ATCA40G, ATCA100G (KR), XFI, SFI, SFP2, Infinyband, Interlaken etc' up to 56Gbps per lane, and of course DDR3 DDR3L DDR4 DDR5, EMMC, RGMII, MIPI, and PAM4 112Gbps Ethernet etc.
High Speed Backplane Design
The signals traveling through backplanes and line cards have speeded up to Giga Hertz from several hundred Mega Hertz. To catch up with its speed, bus architecture has evolved from parallel to serial. While consumers enjoy the broadband internet surfing and smaller access devices, electronic designers are challenged with high performance requirements and tight margin for PCBs and packages. To ensure short Time To Market, they often have to control impedance of PCB traces, take serious consideration in Vias placement, minimize cross-talk between signals, or run complete system simulation.
We provide:
Complete solution to backplane, high-speed interconnect design
Consultation on backplane, high-speed interconnect design
Debugging services in backplane, high-speed interconnect design
Signal Integrity Analysis
For high speed system, signal integrity has come to be an outstanding issue. Signal integrity analysis for high speed IO interfaces is critical for the products to function as they are designed to. We provide:
High-speed channel analysis: chip to chip signaling analysis
Accurate frequency domain model for components
Worst case analysis taking into account manufacture tolerance
System simulation with both transistor buffers and IBIS model
Recommendation of system topology
Recommendation of package type, connectors
Layout design guideline
Recommendation of equalization strategy for IO designs
Power Integrity Analysis
With transistors switching faster, electronic devices become sensitive to power supply noise. It is not rare for incompetent power design to cause system failure. One of the trouble-makers is Simultaneous Switching Noise (SSN), which increases jitter, degrades other timing indicators and triggers logic errors in worse cases. For the device to meet design target, SSN needs to be restrained within allowable amount by choosing the right stack-up, implementing proper power/ground plane layout and decoupling techniques.
Our experience in power delivery network design, modeling, analysis and optimization extends to IC, package, and PCB designs in various applications – computing, communications, automobile, medical care, aviation, etc. We provide:
PCB stack-up design
Power/ground plane layout scheme
Power distribution scheme
Power delivery network model extraction
Simultaneous switching noise analysis and solution
Design optimization for power supply to reduce EMI
Signal quality analysis with power supply noise
Decoupling scheme and via placement
DC analysis and Current density
Passive Component Modeling
Accurate modeling for passive components including discrete components, traces and vias in PCB layout, package interconnects, card connectors. Enables simulations to reveal the true problem of the design. We provide passive component models in various formats:
2D/3D models
S parameter models (Touchstone)
Spice models
Isolation parameters