SI-PI-SIM.com

All your Signal and Power Integrity Simulation needs

We are Guy & Amir
All needed simulation analysis for your Pre-Layout and Post-Layout PCB designs.

Need consultation and/or Simulations services?

Please contact us at:

Amir@si-pi-sim.com

Over 50 accumulative years (25 each :-) of experience in Signal and Power integrity and simulation and design.

Our experience includes tools such as Ansoft (Ansys EM), Cadence SPB, Power-Integrity, SigXplorer, Pspice, MENTOR (Siemens) Hyperlynx , ANSIS SI-Wave, Q3D, HFSS, HFSS_LO, ADS, Synopsys HSpice, Polar Si9000, IBIS, IBIS-AMI, Touchstone/S-PARAM formats. COM, JCOM criteria and more.

We are based in Israel, helping with designs all over the world.

Waveforms and some Full Wave 3D modeling examples below ↓ 

Full Wave 3D modeling

DDR4 3200 jitter/timing  management

IBIS AMI 56Gbps PAM4 Channel

IBIS AMI 32Gbps Channel

AMI PRBS13 16Gbps (PCIE GEN4)  default parameters

AMI 10.3Gbps before and after pre-emphasis change

25Gbps in short Megtron4 Channel (2 vias and connector)

HSPICE, EYE @Rx  Virtex7 to Virtex7 12.5Gbps 522 bits 64to66enc

HSPICE, Agawa channel, 6Gbps link over a 50-inch FR4 trace - AFTER eq vs before.

3D Ceramic Package model - built from 2D layout info + wirebonds and pins 

Differential via structure optimization of Return loss

TAGs: Amir Bloch Guy, Jitter, Crosstalk, x-talk, timing, attenuation, eye opening, S-parameters, Touchstone, transmission & insertion loss, reflection, waveform ...